Further adventures of implementing SHA1 encryption on an FPGA
A few years ago, I designed and simulated a SHA1 encryption machine using CMOS logic. I actually built everything using Altera’s FPGA tools, Quartus. With standard propagation of the 7400 series, it worked out to about 1.8MHz max clock speed to prevent race conditions. Implementing the system right in VHDL and running it on… Read More: Further adventures of implementing SHA1 encryption on an FPGA »