Category Archives: SHA1

Unpacking WPA2

As discussed in a previous article, WPA2 encryption is comprised of three different algorithms layered on top of each other. I went over them in a very brief overview, so here is a more in-depth discussion on how I optimised and implemented them on an FPGA. Also linked in that previous article, it’s worth going… Read More: Unpacking WPA2 »

WPA2 HMAC SHA1 PMK FPGA VHDL

Hell yeah, acronyms. Restartin’ dis. I’ve got the old working SHA1 encryption algorithm going. It’s up on GitHub, here. I was waffling between parallel and serial loads and outputs. SHA1 takes a 512 bit input and outputs 160 bits, and no FPGA that I have access to will have that many pins. Here’s a fallacy I got stuck on… Read More: WPA2 HMAC SHA1 PMK FPGA VHDL »

I need another dev kit

Recently, I got given an FPGA development kit to continue working on my SHA1 system. The end-goal is to eventually integrate that into a PCI-E card, but we’ll see how that works out.   The FPGA kit I have is the Digilent Basys2, and it uses a Xilinx Spartan 3E chip. The lowest-tier, 100k gate model.… Read More: I need another dev kit »

Foiled Again

Pretty soon after I wrote that last post, I got sent up north for work for a long while. Which is great, don’t get me wrong, I like money as much as the next guy. It really limits my ability to physically build, though. So I missed the contest entry deadline. Totally not surprised. I’d… Read More: Foiled Again »