As I sit here, riding shotgun in my work truck on the way to a job site, there is very little that I can do to be productive. I feel like I’m wasting my time.
What I can do is set some final goals for my project, and also maybe do some some musing (in the most pretentious language possible).
But first, some background:
As implied, I spend a lot of my time working on the road. That means a lot of cheap motel rooms, and a lot of unreliable internet access. When you’re stuck for the coldest six weeks of the year in the township of Bumfuck, Northern BC, internet access becomes pretty important.
As often as motel wifi is flaky, my internet-enabled devices can usually see a password-protected residential network nearby. Naturally, trying to break into someone else’s router would be immoral, but it does present an interesting problem. How easy would it be to make a portable wifi cracker?
To make a long story short, I decided to make a very fast WPA-PSK brute forcer. “Very fast” is a little misleading here, because despite potentially having the ability to test hundreds of passwords a second, breaking a properly chosen password is not something that can be done while you sit around and twiddle your thumbs. It takes a little longer. Think “aging a good cask of scotch” timeframes.
By this point, the problem has become purely academic. But that’s okay. I decided to do it anyway. But just as I settled in to write some serious VHDL code, the 7400 competition reared its beautiful head.
So I decided to do something slightly insane and drop the FPGA.
I’m designing a CMOS SHA1 encrypter. The PBKBF2 and MAC portion of WPA2’s encryption scheme won’t be done, the SHA1 will stand alone.
Insane quantities of chips aren’t without precedent for me. My final project in school was a poster child for function creep.
Fig 1: This is what happens when you let the team member with Aspergers add “just one more thing”
As I start to get my teeth into this project, I’m coming to the realization (hope) that I don’t have 16 straight hours of soldering in my future. While there are 512 bits for the input, and 160 for a default seed, and then another 160 for the output, and also a clock source that has trigger each stage sequentially- wait. That does seem like a lot of soldering.
Fortunately, my requirements are pretty tightly defined so not a lot of function creep is possible. There’s only the problem of reliably verifying that the board works by passing the 16-word input and reading the 5-word output. I’d use an Arduino and some shift registers, but I don’t have any ATMegas with bootloaders on them. Maybe I’ll use a PIC and RS232 with a MAX232 and some custom Windows software…
Oh man.
I am in trouble.